Xue

DBG_PRG DDR Banks Ethernet Phy FPGA Port 1, Port 3 (DDR, USB) FPGA Port 1, Port 3 DDR, USB FPGA Spartan6 FPGA, Port0, Port2, PROG IF Image Sensor Non volatile memories PSU Snesor PSU USB xue-rnc All sheets
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Sat Sep 25 19:08:24 2010 -0500, 5 days ago

    Connecting image sensor.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Sat Sep 25 13:33:12 2010 -0500, 5 days ago

    Fixing label problems, connecting image sensor.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Thu Sep 9 17:56:28 2010 -0500, 3 weeks ago

    Kicad labels problem.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Sep 6 21:04:29 2010 -0500, 3 weeks ago

    Routing attiny.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Fri Sep 3 12:22:25 2010 -0500, 4 weeks ago

    Routing current sensors.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Fri Sep 3 10:34:54 2010 -0500, 4 weeks ago

    ERC report generated.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Thu Sep 2 12:55:34 2010 -0500, 4 weeks ago

    PSU Modifying.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Tue Aug 31 13:14:56 2010 -0500, 4 weeks ago

    Modifying USB H-D
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 31 08:30:55 2010 -0500, 4 weeks ago

    2.5V current sensor added
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Aug 30 19:48:29 2010 -0500, 4 weeks ago

    Making power source
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 30 10:45:55 2010 -0500, 4 weeks ago

    FPGA has been splited
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Aug 28 22:00:44 2010 -0500, 5 weeks ago

    5V out DC-DC added 5V DC-DC initial placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 26 21:10:05 2010 -0500, 5 weeks ago

    fix
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 26 19:32:08 2010 -0500, 5 weeks ago

    FAN4010 added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 26 00:41:55 2010 -0500, 5 weeks ago

    usb device connector added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Wed Aug 25 23:02:30 2010 -0500, 5 weeks ago

    DC-DC 1.2 and 3.3 routed
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Wed Aug 25 14:24:48 2010 -0500, 5 weeks ago

    Routing DDR-2
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 24 23:30:39 2010 -0500, 5 weeks ago

    added copper pours
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 24 10:16:32 2010 -0500, 5 weeks ago

    minor routing progress
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 24 06:59:29 2010 -0500, 5 weeks ago

    USB A Phy has been routed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 23 23:10:31 2010 -0500, 5 weeks ago

    USB D routing started
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 23 21:51:23 2010 -0500, 5 weeks ago

    USB A routing
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sun Aug 22 20:30:32 2010 -0500, 6 weeks ago

    second usb-host added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sun Aug 22 19:06:02 2010 -0500, 6 weeks ago

    USB phy component has been changed
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Sun Aug 22 17:24:37 2010 -0500, 6 weeks ago

    Routing DDR-1
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sun Aug 22 13:35:28 2010 -0500, 6 weeks ago

    debug+prog connector added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sun Aug 22 08:24:21 2010 -0500, 6 weeks ago

    NAND flash routed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Aug 21 18:07:32 2010 -0500, 6 weeks ago

    nand routing just started
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Aug 21 16:38:23 2010 -0500, 6 weeks ago

    s6 to eth-phy connections has been completed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Aug 21 07:17:22 2010 -0500, 6 weeks ago

    ddr-vref improved placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 20 20:06:53 2010 -0500, 6 weeks ago

    some eth-phy to s6 nets has been routed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 20 19:10:05 2010 -0500, 6 weeks ago

    some eth-phy to s6 nets has been routed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 20 18:10:16 2010 -0500, 6 weeks ago

    some eth-phy to s6 nets has been routed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 19 08:51:56 2010 -0500, 6 weeks ago

    PSU ICs has been selected
>>> Andres Calderon <andres.calderon@emqbit.com>
    Wed Aug 18 22:09:52 2010 -0500, 6 weeks ago

    3.3v dc-dc added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 17 19:36:33 2010 -0500, 6 weeks ago

    fpga decoupling cap. placement improved
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 17 19:04:05 2010 -0500, 6 weeks ago

    ddr terminators placment
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 23:30:34 2010 -0500, 6 weeks ago

    DDR0 termaintor placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 22:48:30 2010 -0500, 6 weeks ago

    DDR0 termaintor placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 21:49:00 2010 -0500, 6 weeks ago

    PSU controller added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 21:09:50 2010 -0500, 6 weeks ago

    PSU sheet added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 20:56:08 2010 -0500, 6 weeks ago

    ddr termination placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 19:36:21 2010 -0500, 6 weeks ago

    terminal resistors placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 19:06:33 2010 -0500, 6 weeks ago

    terminal resistors placement
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Aug 16 16:49:57 2010 -0500, 6 weeks ago

    Library path fixed
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Aug 16 16:32:29 2010 -0500, 6 weeks ago

    Series resistors (DDR) added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 16 13:13:20 2010 -0500, 6 weeks ago

    attiny.lib added
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Aug 16 11:57:16 2010 -0500, 6 weeks ago

    General issues corrected
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Aug 14 08:23:56 2010 -0500, 7 weeks ago

    fixed FPGA component bug
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Aug 14 08:15:48 2010 -0500, 7 weeks ago

    fixed xc6slx45fgg484.lib  error
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 13 22:09:52 2010 -0500, 7 weeks ago

    improved placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 13 18:38:38 2010 -0500, 7 weeks ago

    decoupling nand flash added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 13 18:20:50 2010 -0500, 7 weeks ago

    decoupling DDR cap. placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 13 17:34:12 2010 -0500, 7 weeks ago

    VCC fixed
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 13 15:42:35 2010 -0500, 7 weeks ago

    spi memory added
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Fri Aug 13 11:24:39 2010 -0500, 7 weeks ago

    FPGA decoupling capacitors
>>> Andres Calderon <andres.calderon@emqbit.com>
    Fri Aug 13 09:27:10 2010 -0500, 7 weeks ago

    usb added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 12 21:12:14 2010 -0500, 7 weeks ago

    fix
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 12 17:18:08 2010 -0500, 7 weeks ago

    fix
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 12 16:12:57 2010 -0500, 7 weeks ago

    fixed placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Thu Aug 12 08:12:03 2010 -0500, 7 weeks ago

    FB added to USB host
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Tue Aug 10 21:25:32 2010 -0500, 7 weeks ago

    Fixing USB connections
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 10 18:51:35 2010 -0500, 7 weeks ago

    VCCs connected
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 10 18:27:44 2010 -0500, 7 weeks ago

    only a test
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 10 18:09:38 2010 -0500, 7 weeks ago

    SD connector attached to th S6
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 10 17:38:37 2010 -0500, 7 weeks ago

    DDR de-coupling caps. added
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 9 22:25:05 2010 -0500, 7 weeks ago

    early placement
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 9 20:21:14 2010 -0500, 7 weeks ago

    annotate
>>> Andres Calderon <andres.calderon@emqbit.com>
    Mon Aug 9 20:16:50 2010 -0500, 7 weeks ago

    ddr component changed
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Aug 9 19:12:59 2010 -0500, 7 weeks ago

    Adding librarys.
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Mon Aug 9 15:37:18 2010 -0500, 7 weeks ago

    Ethernet-phy and USB connected to FPGA
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sun Aug 8 22:53:21 2010 -0500, 7 weeks ago

    more fpga ddr lines has been connected
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Sun Aug 8 17:54:09 2010 -0500, 8 weeks ago

    USB and MICROSD footprints added
>>> Juan64Bits <juan64bits@Maximus.(none)>
    Sun Aug 8 12:15:44 2010 -0500, 8 weeks ago

    Phy
>>> Andres Calderon <andres.calderon@emqbit.com>
    Wed Aug 4 20:50:31 2010 -0500, 8 weeks ago

    ddr address and data has been conected to the FPGA
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Aug 3 21:23:17 2010 -0500, 8 weeks ago

    ddr mobile replaced by ddr
>>> Andres Calderon <andres.calderon@emqbit.com>
    Wed Jul 28 06:48:02 2010 -0500, 9 weeks ago

    only one wire connected
>>> Andres Calderon <andres.calderon@emqbit.com>
    Tue Jul 27 20:09:20 2010 -0500, 9 weeks ago

    some ethernet phy conections
>>> Andres Calderon <andres.calderon@emqbit.com>
    Sat Jul 24 06:58:53 2010 -0500, 10 weeks ago

    initial import

2010-09-30 13:18:54 UTC